// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

`timescale 1 ps / 1 ps
`default_nettype none

module pfr_top (
    input wire CLK_25M_OSC_PFR_FPGA,
    input wire PWRGD_P1V2_MAX10_AUX_SCM_PLD_R,
    inout wire SMB_CPLD_UPDATE_PFR_SCL_LVC3_R,
    inout wire SMB_CPLD_UPDATE_PFR_SDA_LVC3_R,
    output wire RST_SPI_PFR_CPU0_RESET_N,
    output wire SPI_OPFR_CPU0_CS0_LVC18_N,
    output wire SPI_OPFR_CPU0_CS1_LVC18_N,
    input wire SPI_CPU0_PFR_MON_CS0_SWAP_N,
    input wire SPI_CPU0_PFR_MON_CS1_SWAP_N,
    output wire FM_PFR_CPU0_SPI_MASTERSEL,
    inout wire SPI_CLK_OPFR_CPU0_LVC18,
    inout wire SPI_OPFR_CPU0_IO0_LVC18_R,
    inout wire SPI_OPFR_CPU0_IO1_LVC18_R,
    inout wire SPI_OPFR_CPU0_IO2_LVC18_R,
    inout wire SPI_OPFR_CPU0_IO3_LVC18_R,
    input wire SPI_CPU0_PFR_MON_CLK,
    inout wire SPI_CPU0_PFR_MON_IO0,
    inout wire SPI_CPU0_PFR_MON_IO1,
    inout wire SPI_CPU0_PFR_MON_IO2,
    inout wire SPI_CPU0_PFR_MON_IO3,
    output wire RST_SPI_PFR_CPU1_N,
    output wire SPI_CPU1_PFR_CTRL_CS_N,
    output wire SPI_CPU1_PFR_CTRL_CS1_N,
    input wire SPI_CPU1_PFR_MON_CS0_N,
    input wire SPI_CPU1_PFR_MON_CS1_N,
    output wire FM_PFR_CPU1_SPI_MASTERSEL,
    inout wire SPI_CPU1_PFR_CTRL_CLK,
    inout wire SPI_CPU1_PFR_CTRL_MOSI,
    inout wire SPI_CPU1_PFR_CTRL_MISO,
    inout wire SPI_CPU1_PFR_CTRL_IO2,
    inout wire SPI_CPU1_PFR_CTRL_IO3,
    input wire SPI_CPU1_PFR_MON_CLK,
    inout wire SPI_CPU1_PFR_MON_IO0,
    inout wire SPI_CPU1_PFR_MON_IO1,
    inout wire SPI_CPU1_PFR_MON_IO2,
    inout wire SPI_CPU1_PFR_MON_IO3,
    output wire RST_PFR_BMC_SPI_RESET_N,
    output wire SPI_OPFR_BMC_CS0_LVC3_N,
    input wire SPI_BMC_PFR_MON_CS0_N,
    output wire FM_PFR_BMC_SPI_MASTERSEL,
    inout wire SPI_CLK_OPFR_BMC_LVC3,
    inout wire SPI_OPFR_BMC_IO0_LVC3_R,
    inout wire SPI_OPFR_BMC_IO1_LVC3_R,
    inout wire SPI_OPFR_BMC_IO2_LVC3_R,
    inout wire SPI_OPFR_BMC_IO3_LVC3_R,
    input wire SPI_BMC_PFR_MON_CLK,
    inout wire SPI_BMC_PFR_MON_IO0,
    inout wire SPI_BMC_PFR_MON_IO1,
    inout wire SPI_BMC_PFR_MON_IO2,
    inout wire SPI_BMC_PFR_MON_IO3,
    output wire SPI_PFR_CS0_N,
    inout wire SPI_PFR_CLK,
    inout wire SPI_PFR_IO0,
    inout wire SPI_PFR_IO1,
    inout wire SPI_PFR_IO2,
    inout wire SPI_PFR_IO3,
    output wire RST_SPI_PFR_RESET_N,
    inout wire SMB_PMBUS1_BMC_LVC3_SCL,
    inout wire SMB_PMBUS1_BMC_LVC3_SDA,
    inout wire SMB_PMBUS1_SCM_SCL_R,
    inout wire SMB_PMBUS1_SCM_SDA_R,
    inout wire SMB_PMBUS2_BMC_LVC3_SCL,
    inout wire SMB_PMBUS2_BMC_LVC3_SDA,
    inout wire SMB_PMBUS2_SCM_SCL_R,
    inout wire SMB_PMBUS2_SCM_SDA_R,
    inout wire SMB_HSBP_BMC_SCL_LVC3,
    inout wire SMB_HSBP_BMC_SDA_LVC3,
    inout wire SMB_HSBP_SCM_SCL_LVC3_R1,
    inout wire SMB_HSBP_SCM_SDA_LVC3_R1,
    inout wire SMB_PCIE_PFR_SCL_LVC3_R1,
    inout wire SMB_PCIE_PFR_SDA_LVC3_R1,
    inout wire I3C_PFR_BMC_SCL,
    inout wire I3C_PFR_BMC_SDA,
    output wire FM_I3C_PFR_BMC_PUR_EN,
    inout wire I3C_PFR_PCIE_SCL,
    inout wire I3C_PFR_PCIE_SDA,
    output wire FM_I3C_PFR_PCIE_PUR_EN,
    inout wire I3C_PFR_MNG_SCL,
    inout wire I3C_PFR_MNG_SDA,
    output wire FM_I3C_PFR_MNG_PUR_EN,
    output wire FM_PFR_MNG_SEL,
    output wire FM_PFR_PCIE_SEL,
    inout wire SMB_PFR_RFID_SCL,
    inout wire SMB_PFR_RFID_SDA,
    input wire PWRGD_AUX_PWRGD_CPU0,
    input wire PWRGD_AUX_PWRGD_CPU1,
    output wire PWRGD_AUX_PWRGD_PFR_CPU0,
    output wire PWRGD_AUX_PWRGD_PFR_CPU1,
    input wire RST_PLTRST_CPU0_N,
    input wire RST_PLTRST_CPU1_N,
    output wire RST_PLTRST_CPU0_PFR_LVC3_N,
    output wire RST_PLTRST_CPU1_PFR_LVC3_N,
    output wire PFR_CPU0_RTC_RST_N,
    output wire PFR_CPU1_RTC_RST_N,
    output wire RST_SRST_BMC_SCM_FPGA_N,
    input wire RST_SRST_BMC_PFR_N,
    output wire RST_PFR_BMC_EXTRST_N,
    input wire FP_ID_LED_BMC_N,
    input wire FP_LED_STATUS_GREEN_BMC_N,
    input wire FP_LED_STATUS_AMBER_BMC_N,
    input wire FP_BMC_PWR_BTN_N,
    output wire FP_ID_LED_N,
    output wire FP_LED_STATUS_GREEN_N,
    output wire FP_LED_STATUS_AMBER_N,
    output wire FP_PWR_BTN_PFR_N,
    input wire FM_PFR_DEBUG_JUMPER,
    input wire FM_PFR_FORCE_RECOVERY_N,
    input wire FM_HPFR_IN,
    input wire FM_HPFR_LEGACY,
    input wire FM_HPFR_ACTIVE,
    output wire FM_HPFR_OUT,
    output wire SGPIO_PFR_DOUT,
    output wire SGPIO_PFR_CLK,
    input wire SGPIO_PFR_DIN,
    output wire SGPIO_PFR_LD_N,
    input wire FM_PFR_CC_RSVD_0,
    input wire FM_PFR_CC_RSVD_1,
    output wire FM_PFR_CC_RSVD_2,
    output wire FM_PFR_CC_RSVD_3,
    output wire FM_PFR_CC_RSVD_4,
    output wire FM_PFR_SMB_CPLD_UPDATE_SEL

);

    // Clocks and resets
    wire pll_locked;
    wire clk2M;
    wire clk50M;
    wire clk100M;
    wire sys_clk;
    wire spi_clk;
    wire clk2M_reset_sync_n;
    wire clk50M_reset_sync_n;
    wire sys_clk_reset_sync_n;
    wire spi_clk_reset_sync_n;
    wire clk100M_reset_sync_n;
    
    logic PWRGD_P1V2_MAX10_AUX_SCM_PLD_R_filtered;
    
    async_input_filter #(
        .NUM_METASTABILITY_REGS (2),
        .NUM_FILTER_REGS        (2)
    ) sync_master_scl_inst (
        .clock                  ( CLK_25M_OSC_PFR_FPGA ),
        .ia_async_in            ( PWRGD_P1V2_MAX10_AUX_SCM_PLD_R ),
        .o_sync_out             ( PWRGD_P1V2_MAX10_AUX_SCM_PLD_R_filtered ),
        .o_rising_edge          (  ),
        .o_falling_edge         (  )
    );
    
    // Clocks and reset generator
    pfr_sys_clocks_reset u_pfr_sys_clocks_reset (
        .refclk(CLK_25M_OSC_PFR_FPGA),
        .pll_reset(!PWRGD_P1V2_MAX10_AUX_SCM_PLD_R_filtered),
        .pll_locked(pll_locked),
        .clk2M(clk2M),
        .clk50M(clk50M),
        .clk100M(clk100M),
        .sys_clk(sys_clk),
        .spi_clk(spi_clk),
        .clk2M_reset_sync_n(clk2M_reset_sync_n),
        .clk50M_reset_sync_n(clk50M_reset_sync_n),
        .sys_clk_reset_sync_n(sys_clk_reset_sync_n),
        .spi_clk_reset_sync_n(spi_clk_reset_sync_n),
        .clk100M_reset_sync_n(clk100M_reset_sync_n)
    );
    
    pfr_core u_core (

        .clk2M(clk2M),
        .clk50M(clk50M),
        .clk100M(clk100M),
        .sys_clk(sys_clk),
        .spi_clk(spi_clk),
        .clk2M_reset_sync_n(clk2M_reset_sync_n),
        .clk50M_reset_sync_n(clk50M_reset_sync_n),
        .sys_clk_reset_sync_n(sys_clk_reset_sync_n),
        .spi_clk_reset_sync_n(spi_clk_reset_sync_n),
        .clk100M_reset_sync_n(clk100M_reset_sync_n),

        .SMB_CPLD_UPDATE_PFR_SCL_LVC3_R(SMB_CPLD_UPDATE_PFR_SCL_LVC3_R),
        .SMB_CPLD_UPDATE_PFR_SDA_LVC3_R(SMB_CPLD_UPDATE_PFR_SDA_LVC3_R),
        .RST_SPI_PFR_CPU0_RESET_N(RST_SPI_PFR_CPU0_RESET_N),
        .SPI_OPFR_CPU0_CS0_LVC18_N(SPI_OPFR_CPU0_CS0_LVC18_N),
        .SPI_OPFR_CPU0_CS1_LVC18_N(SPI_OPFR_CPU0_CS1_LVC18_N),
        .SPI_CPU0_PFR_MON_CS0_SWAP_N(SPI_CPU0_PFR_MON_CS0_SWAP_N),
        .SPI_CPU0_PFR_MON_CS1_SWAP_N(SPI_CPU0_PFR_MON_CS1_SWAP_N),
        .FM_PFR_CPU0_SPI_MASTERSEL(FM_PFR_CPU0_SPI_MASTERSEL),
        .SPI_CLK_OPFR_CPU0_LVC18(SPI_CLK_OPFR_CPU0_LVC18),
        .SPI_OPFR_CPU0_IO0_LVC18_R(SPI_OPFR_CPU0_IO0_LVC18_R),
        .SPI_OPFR_CPU0_IO1_LVC18_R(SPI_OPFR_CPU0_IO1_LVC18_R),
        .SPI_OPFR_CPU0_IO2_LVC18_R(SPI_OPFR_CPU0_IO2_LVC18_R),
        .SPI_OPFR_CPU0_IO3_LVC18_R(SPI_OPFR_CPU0_IO3_LVC18_R),
        .SPI_CPU0_PFR_MON_CLK(SPI_CPU0_PFR_MON_CLK),
        .SPI_CPU0_PFR_MON_IO0(SPI_CPU0_PFR_MON_IO0),
        .SPI_CPU0_PFR_MON_IO1(SPI_CPU0_PFR_MON_IO1),
        .SPI_CPU0_PFR_MON_IO2(SPI_CPU0_PFR_MON_IO2),
        .SPI_CPU0_PFR_MON_IO3(SPI_CPU0_PFR_MON_IO3),
        .RST_SPI_PFR_CPU1_N(RST_SPI_PFR_CPU1_N),
        .SPI_CPU1_PFR_CTRL_CS_N(SPI_CPU1_PFR_CTRL_CS_N),
        .SPI_CPU1_PFR_CTRL_CS1_N(SPI_CPU1_PFR_CTRL_CS1_N),
        .SPI_CPU1_PFR_MON_CS0_N(SPI_CPU1_PFR_MON_CS0_N),
        .SPI_CPU1_PFR_MON_CS1_N(SPI_CPU1_PFR_MON_CS1_N),
        .FM_PFR_CPU1_SPI_MASTERSEL(FM_PFR_CPU1_SPI_MASTERSEL),
        .SPI_CPU1_PFR_CTRL_CLK(SPI_CPU1_PFR_CTRL_CLK),
        .SPI_CPU1_PFR_CTRL_MOSI(SPI_CPU1_PFR_CTRL_MOSI),
        .SPI_CPU1_PFR_CTRL_MISO(SPI_CPU1_PFR_CTRL_MISO),
        .SPI_CPU1_PFR_CTRL_IO2(SPI_CPU1_PFR_CTRL_IO2),
        .SPI_CPU1_PFR_CTRL_IO3(SPI_CPU1_PFR_CTRL_IO3),
        .SPI_CPU1_PFR_MON_CLK(SPI_CPU1_PFR_MON_CLK),
        .SPI_CPU1_PFR_MON_IO0(SPI_CPU1_PFR_MON_IO0),
        .SPI_CPU1_PFR_MON_IO1(SPI_CPU1_PFR_MON_IO1),
        .SPI_CPU1_PFR_MON_IO2(SPI_CPU1_PFR_MON_IO2),
        .SPI_CPU1_PFR_MON_IO3(SPI_CPU1_PFR_MON_IO3),
        .RST_PFR_BMC_SPI_RESET_N(RST_PFR_BMC_SPI_RESET_N),
        .SPI_OPFR_BMC_CS0_LVC3_N(SPI_OPFR_BMC_CS0_LVC3_N),
        .SPI_BMC_PFR_MON_CS0_N(SPI_BMC_PFR_MON_CS0_N),
        .FM_PFR_BMC_SPI_MASTERSEL(FM_PFR_BMC_SPI_MASTERSEL),
        .SPI_CLK_OPFR_BMC_LVC3(SPI_CLK_OPFR_BMC_LVC3),
        .SPI_OPFR_BMC_IO0_LVC3_R(SPI_OPFR_BMC_IO0_LVC3_R),
        .SPI_OPFR_BMC_IO1_LVC3_R(SPI_OPFR_BMC_IO1_LVC3_R),
        .SPI_OPFR_BMC_IO2_LVC3_R(SPI_OPFR_BMC_IO2_LVC3_R),
        .SPI_OPFR_BMC_IO3_LVC3_R(SPI_OPFR_BMC_IO3_LVC3_R),
        .SPI_BMC_PFR_MON_CLK(SPI_BMC_PFR_MON_CLK),
        .SPI_BMC_PFR_MON_IO0(SPI_BMC_PFR_MON_IO0),
        .SPI_BMC_PFR_MON_IO1(SPI_BMC_PFR_MON_IO1),
        .SPI_BMC_PFR_MON_IO2(SPI_BMC_PFR_MON_IO2),
        .SPI_BMC_PFR_MON_IO3(SPI_BMC_PFR_MON_IO3),
        .SPI_PFR_CS0_N(SPI_PFR_CS0_N),
        .SPI_PFR_CLK(SPI_PFR_CLK),
        .SPI_PFR_IO0(SPI_PFR_IO0),
        .SPI_PFR_IO1(SPI_PFR_IO1),
        .SPI_PFR_IO2(SPI_PFR_IO2),
        .SPI_PFR_IO3(SPI_PFR_IO3),
        .RST_SPI_PFR_RESET_N(RST_SPI_PFR_RESET_N),
        .SMB_PMBUS1_BMC_LVC3_SCL(SMB_PMBUS1_BMC_LVC3_SCL),
        .SMB_PMBUS1_BMC_LVC3_SDA(SMB_PMBUS1_BMC_LVC3_SDA),
        .SMB_PMBUS1_SCM_SCL_R(SMB_PMBUS1_SCM_SCL_R),
        .SMB_PMBUS1_SCM_SDA_R(SMB_PMBUS1_SCM_SDA_R),
        .SMB_PMBUS2_BMC_LVC3_SCL(SMB_PMBUS2_BMC_LVC3_SCL),
        .SMB_PMBUS2_BMC_LVC3_SDA(SMB_PMBUS2_BMC_LVC3_SDA),
        .SMB_PMBUS2_SCM_SCL_R(SMB_PMBUS2_SCM_SCL_R),
        .SMB_PMBUS2_SCM_SDA_R(SMB_PMBUS2_SCM_SDA_R),
        .SMB_HSBP_BMC_SCL_LVC3(SMB_HSBP_BMC_SCL_LVC3),
        .SMB_HSBP_BMC_SDA_LVC3(SMB_HSBP_BMC_SDA_LVC3),
        .SMB_HSBP_SCM_SCL_LVC3_R1(SMB_HSBP_SCM_SCL_LVC3_R1),
        .SMB_HSBP_SCM_SDA_LVC3_R1(SMB_HSBP_SCM_SDA_LVC3_R1),
        .SMB_PCIE_PFR_SCL_LVC3_R1(SMB_PCIE_PFR_SCL_LVC3_R1),
        .SMB_PCIE_PFR_SDA_LVC3_R1(SMB_PCIE_PFR_SDA_LVC3_R1),
        .I3C_PFR_BMC_SCL(I3C_PFR_BMC_SCL),
        .I3C_PFR_BMC_SDA(I3C_PFR_BMC_SDA),
        .FM_I3C_PFR_BMC_PUR_EN(FM_I3C_PFR_BMC_PUR_EN),
        .I3C_PFR_PCIE_SCL(I3C_PFR_PCIE_SCL),
        .I3C_PFR_PCIE_SDA(I3C_PFR_PCIE_SDA),
        .FM_I3C_PFR_PCIE_PUR_EN(FM_I3C_PFR_PCIE_PUR_EN),
        .I3C_PFR_MNG_SCL(I3C_PFR_MNG_SCL),
        .I3C_PFR_MNG_SDA(I3C_PFR_MNG_SDA),
        .FM_I3C_PFR_MNG_PUR_EN(FM_I3C_PFR_MNG_PUR_EN),
        .FM_PFR_MNG_SEL(FM_PFR_MNG_SEL),
        .FM_PFR_PCIE_SEL(FM_PFR_PCIE_SEL),
        .SMB_PFR_RFID_SCL(SMB_PFR_RFID_SCL),
        .SMB_PFR_RFID_SDA(SMB_PFR_RFID_SDA),
        .PWRGD_AUX_PWRGD_CPU0(PWRGD_AUX_PWRGD_CPU0),
        .PWRGD_AUX_PWRGD_CPU1(PWRGD_AUX_PWRGD_CPU1),
        .PWRGD_AUX_PWRGD_PFR_CPU0(PWRGD_AUX_PWRGD_PFR_CPU0),
        .PWRGD_AUX_PWRGD_PFR_CPU1(PWRGD_AUX_PWRGD_PFR_CPU1),
        .RST_PLTRST_CPU0_N(RST_PLTRST_CPU0_N),
        .RST_PLTRST_CPU1_N(RST_PLTRST_CPU1_N),
        .RST_PLTRST_CPU0_PFR_LVC3_N(RST_PLTRST_CPU0_PFR_LVC3_N),
        .RST_PLTRST_CPU1_PFR_LVC3_N(RST_PLTRST_CPU1_PFR_LVC3_N),
        .PFR_CPU0_RTC_RST_N(PFR_CPU0_RTC_RST_N),
        .PFR_CPU1_RTC_RST_N(PFR_CPU1_RTC_RST_N),
        .RST_SRST_BMC_SCM_FPGA_N(RST_SRST_BMC_SCM_FPGA_N),
        .RST_SRST_BMC_PFR_N(RST_SRST_BMC_PFR_N),
        .RST_PFR_BMC_EXTRST_N(RST_PFR_BMC_EXTRST_N),
        .FP_ID_LED_BMC_N(FP_ID_LED_BMC_N),
        .FP_LED_STATUS_GREEN_BMC_N(FP_LED_STATUS_GREEN_BMC_N),
        .FP_LED_STATUS_AMBER_BMC_N(FP_LED_STATUS_AMBER_BMC_N),
        .FP_BMC_PWR_BTN_N(FP_BMC_PWR_BTN_N),
        .FP_ID_LED_N(FP_ID_LED_N),
        .FP_LED_STATUS_GREEN_N(FP_LED_STATUS_GREEN_N),
        .FP_LED_STATUS_AMBER_N(FP_LED_STATUS_AMBER_N),
        .FP_PWR_BTN_PFR_N(FP_PWR_BTN_PFR_N),
        .FM_PFR_DEBUG_JUMPER(FM_PFR_DEBUG_JUMPER),
        .FM_PFR_FORCE_RECOVERY_N(FM_PFR_FORCE_RECOVERY_N),
        .FM_HPFR_IN(FM_HPFR_IN),
        .FM_HPFR_LEGACY(FM_HPFR_LEGACY),
        .FM_HPFR_ACTIVE(FM_HPFR_ACTIVE),
        .FM_HPFR_OUT(FM_HPFR_OUT),
        .SGPIO_PFR_DOUT(SGPIO_PFR_DOUT),
        .SGPIO_PFR_CLK(SGPIO_PFR_CLK),
        .SGPIO_PFR_DIN(SGPIO_PFR_DIN),
        .SGPIO_PFR_LD_N(SGPIO_PFR_LD_N),
        .FM_PFR_CC_RSVD_0(FM_PFR_CC_RSVD_0),
        .FM_PFR_CC_RSVD_1(FM_PFR_CC_RSVD_1),
        .FM_PFR_CC_RSVD_2(FM_PFR_CC_RSVD_2),
        .FM_PFR_CC_RSVD_3(FM_PFR_CC_RSVD_3),
        .FM_PFR_CC_RSVD_4(FM_PFR_CC_RSVD_4),
        .FM_PFR_SMB_CPLD_UPDATE_SEL(FM_PFR_SMB_CPLD_UPDATE_SEL)

    );



endmodule
